1. Field of the Invention
The invention relates generally to a method and apparatus for reducing the effects of parasitic bipolar discharge of silicon-on-insulator (SOI) electronic devices. More specifically, the invention relates to eliminating the unwanted effect of parasitic bipolar discharge of SOI field effect transistors (FET) in dynamic logic circuits.
2. Description of Related Art
Silicon-on-insulator (SOI) technology is an enhanced silicon technology currently being utilized to increase the performance of digital logic circuits. Utilizing SOI technology designers can increase the speed of digital logic integrated circuits while reducing their overall power consumption. These advances in technology will lead to the development of more complex and faster computer integrated circuits that operate with less power.
In recent years Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) integrated circuits and Complementary Metal Oxide Semiconductor (CMOS) FETs have gained popularity and are the most widely used type of integrated circuit technology. Today, CMOS electronic devices provide advantages of higher operating speeds, smaller size, lower power consumption, and are increasingly becoming cheaper to manufacture as a result of smaller component size, higher manufacturing production yields per semiconductor wafer, and larger wafer sizes. The most popular integrated circuit devices manufactured utilizing CMOS technology are microprocessors, memory, and digital logic circuits.
Traditional MOS and CMOS semiconductors consist of a metal on an oxide layer that is placed on a silicon substrate. The added impurities in the silicon substrate enable these devices to operate as transistors. On the other hand, SOI semiconductors include a thin layer of silicon placed on top of an insulator, such as silicon oxide or glass, and a MOS transistor built on top of this structure. The main advantage of constructing the MOS Transistor on top of an insulator layer is to reduce the internal capacitance of the transistor. This is accomplished by placing the insulator oxide layer between the silicon substrate and the impurities required for the device to operate as a transistor. Reducing the internal Capacitance of the transistor increases its operating speed. Therefore, with SOI technology faster MOS transistors can be manufactured resulting in higher performance semiconductors to fuel emerging needs for faster electronic devices.
SOI technology has several drawbacks. An inherent drawback of placing a MOS transistor on top of a SOI layer is that the MOS transistor is actually placed in parallel with a bipolar junction transistor. If enough current is passed through the MOS transistor, the parasitic bipolar transistor will turn on. This causes an unwanted effect called bipolar discharge and lowers the performance of the MOS transistor.
High speed CMOS circuits often employ a domino circuit technique that utilizes pre-charging to improve the gate speeds of the transistors. Dynamic circuit nodes are pre-charged during each clock cycle to a certain level. The problem with SOI FETs is that the parasitic bipolar transistor causes bipolar discharge. This is undesirable because it causes an unintended loss of charge on the drain nodes of the dynamic circuit.
Normally, parasitic bipolar action does not manifest itself in conventional, bulk, MOS transistors because the base of the bipolar transistor is always kept at ground potential, keeping the bipolar off. In SOI, the body of the MOS FET device, or base of the bipolar transistor, is floating and can be charged high by junction leakages induced when the drain and source terminals of the MOS FET are at a high potential. Subsequently, if the source is pulled to a low potential, the trapped charge in the base area is available as parasitic base current. The parasitic base current activates the bipolar transistor and generates a collector current at the drain terminal of the MOS FET. The unintentional loss of charge could lead to system failure, for example, by erroneously switching logic state.
As a result, it can be seen that there is a need to minimize the effect of parasitic bipolar transistors in parallel with MOS transistors in dynamic logic circuits.
The present invention relates generally to a method and apparatus for reducing the effects of parasitic bipolar discharge of silicon-on-insulator (SOI) devices. More specifically, the present invention relates to eliminating the unwanted effect of parasitic bipolar discharge of SOI field effect transistors (FET) in dynamic logic circuits.
In accordance with a preferred embodiment, the present invention provides an apparatus and method to overcome the unwanted effects of parasitic bipolar discharge in silicon-on-insulator (SOI) field effect transistors (FET) by inserting a discharging device at intermediate nodes of the dynamic circuit to keep the voltages at the sources at a low potential. Furthermore, the discharging device is turned on prior to discharging the nodes of the SOI FET in domino logic circuits to disable the body charge of the SOI FET.
In one embodiment, the present invention provides an apparatus for eliminating parasitic bipolar transistor action in a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) device comprising: a SOI electronic device; and an active discharging device coupled to said SOI electronic device, whereby the parasitic bipolar transistor is deactivated.
In another embodiment, the present invention provides, a method of eliminating parasitic bipolar transistor action in a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) device, the method comprising: controlling the conduction of an active discharging device, said active discharging device being coupled to said SOI device, whereby the parasitic bipolar transistor is deactivated.
In yet another embodiment, the present invention provides a Silicon on Insulator(SOI) dynamic logic circuit having an input, an output, and a clock, comprising: a plurality of stacked SOI Metal Oxide Semiconductor (MOS) transistors interconnected to perform a predetermined logic function defining a common node and a plurality of intermediate nodes, said common node being coupled to a pre-charging device and said intermediate node having a corresponding input coupled to said stacked transistors; and a plurality of active discharging transistors interconnected between said intermediate nodes and any one of said corresponding input to said stacked transistors.
In a further embodiment, the present invention provides a method of eliminating parasitic bipolar transistor action in a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) dynamic logic circuit having an input an output, and a clock, comprising a plurality of stacked SOI Metal Oxide Semiconductor (MOS) transistors interconnected to perform a predetermined logic function defining a common node and a plurality of intermediate nodes, said common node being coupled to a pre-charging device and said intermediate nodes having a corresponding input coupled to said stacked transistors; and a plurality of active discharging transistors interconnected between said intermediate nodes and any one of said corresponding inputs to said stacked transistors, the method comprising: controlling the conduction of said active discharging transistors during a pre-charge cycle; and actively discharging said intermediate nodes of the SOI stacked transistors, whereby the parasitic bipolar transistors are deactivated and the charge at said common node is maintained at a predetermined level.
These and various other features and advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description and corresponding drawings. As will be realized, the invention is capable of modification without departing from the invention. Accordingly, the drawing and description are to be regarded as being illustrative in nature, and not as restrictive.